BECKHOFF ET1100 - Manual (Page 31)

EtherCAT IP Core for Altera FPGAs
Slave Controller – Application Note FAQ 27
4.3 Hardware issues
If the hardware is not working, the following functions should be tested, e.g., by routing signals to
LEDs or using SignalTap II or external measurement equipment.

Reset: polarity issues are common, probe exactly the signal which enters the IP Core.

Clock: Are all clocks connected, valid and synchronous (25 MHz and 100 MHz)? Is the PLL
locked?

Turn off MI link detection and configuration for testing if the PHY does not need to be re-
configured.

Check in the reports if all FPGA pins are located correctly.

Is the Timing report error-free?
4.4 OpenCore Plus design stops operating too early
If you want to test the OpenCore Plus design for about one hour without JTAG connection, follow
these steps:
1. Program the FPGA (the OpenCore Plus window appears after programming)
2. Disconnect the JTAG interface.
3. Accept the OpenCore Plus window notice.
If you accept the OpenCore Plus window notice before disconnecting the JTAG, Quartus II will disable
the logic immediately. By following the above steps, the one hour operation is possible.