BECKHOFF ET1100 - Manual (Page 41)

EtherCAT IP Core for Xilinx FPGAs
Slave Controller – Application Note FAQ 37
5.3.2 Place & Route
5.3.2.1 CLOCK_DEDICATED_ROUTE=FALSE with SPI reference design
The SPI_DI and SPI_SEL signals are used as clock inputs for a few control logic registers. Since
these signals are not placed on dedicated clock inputs
– which is not required –, Xilinx ISE sometimes
issues an error, which needs to be suppressed.
Messages
Phase 4.2 Initial Clock and IO Placement
.................
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component is placed at site . The IO component
is placed at site . This will not allow the use of the fast path between the IO and the Clock
buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this
override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to override this clock rule.
< NET "PDI_SPI_SEL" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component is placed at site . The IO component
is placed at site . This will not allow the use of the fast path between the IO and the Clock
buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this
override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to override this clock rule.
< NET "PDI_SPI_DI" CLOCK_DEDICATED_ROUTE = FALSE; >
Solution for ISE/EDK 10/11/12 with Spartan-3x devices
Add the following constraints to the UCF file:
Net PDI_SPI_SEL CLOCK_DEDICATED_ROUTE = FALSE;
Net PDI_SPI_DI CLOCK_DEDICATED_ROUTE = FALSE;
Solution for ISE/EDK 11.3 with Spartan-6 devices
Add the following constraints to the UCF file:
PIN "PDI_SPI_DI_BUFGP.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "PDI_SPI_SEL_BUFGP.O" CLOCK_DEDICATED_ROUTE = FALSE;
Solution for ISE/EDK 11.4-12.4 with Spartan-6 devices
Add the following constraints to the UCF file:
PIN "PDI_SPI_DI_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "PDI_SPI_SEL_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
Solution for ISE/EDK 13.1
In this version, no CLOCK_DEDICATED_ROUTE=FALSE constraint is required, since the SPI_CLK
location is not considered an error any more.