BECKHOFF ET1100 - Manual (Page 26)

EtherCAT IP Core for Altera FPGAs
22 Slave Controller – Application Note FAQ
4.2.2.4 Important logic parts or I/O signals are optimized away, hardware does not work
If important logic blocks or I/O signals are optimized away, please check if every signal of the
EtherCAT IP Core is connected, especially the input signals. Altera Quartus II adds default values for
all input signals of a MegaFunction. If such an input signal remains unconnected, no error will be
generated, but some logic up to I/Os will be optimized away because the input is static. This is an
Altera Quartus II issue.
As an example, have a look at the generated VHDL source code of an EtherCAT MegaFunction:
entity ethercat_digitalio is
port ( NRESET : in std_logic:= '0' ;
CLK25 : in std_logic:= '0';
CLK100 : in std_logic:= '0';
PROM_CLK : out std_logic;
PROM_SIZE : in std_logic:= '0';
PROM_DATA_IN : in std_logic:= '0';
[...]
Figure 9: MegaFunction entity with default values
If nRESET would be left unconnected, the whole IP Core would remain in reset state. If CLK100 would
be left unconnected, only parts of the design would be functional. Depending on the signal, many
different error scenarios can occur.