BECKHOFF ET1100 - Manual (Page 14)

General Issues
10 Slave Controller – Application Note FAQ
3.13 PDI Performance
The PDI interface performance cannot be compared with the performance of a simple dual-ported
memory, mainly because of the SyncManagers. The SyncManager buffer mechanism coordinates
EtherCAT and PDI access to the memory and registers by the means of buffer re-mapping,
enabling/disabling accesses, and interrupt/error handling. Especially the dependency between
EtherCAT frame processing and PDI reduces PDI performance.
The theoretical maximum throughput of any PDI is (1 Byte / 80 ns) = 12.5 Mbyte/s (equal to the
maximum Ethernet throughput). Additional latency is required for synchronization (clock domain
crossing, EtherCAT frame start) and read/write collision detection.
The datasheet figures are worst case timing, min./max. and average read/write times for the
asynchronous µC PDI while using the BUSY signal are (ET1100, preliminary):
Read 16 bit: min. 195 ns, average 235 ns, max. 575 ns
Write 16 bit: min. 160 ns, average 200 ns, max. 280 ns
The maximum read time includes a postponed 16 bit write access, a 16 bit read access, phase
alignment and read/write collision. A µController has to cope with this maximum latency, but it is not
the average latency! If large amounts of data are to be transferred in one direction (either read or
write), the latency is coming close to the average value.
All PDIs are using the same internal interface, thus the maximum throughputs of the PDIs are very
similar, and even the on-
chip bus PDIs are comparable. That’s because they are all limited by the
internal PDI/SyncManager realization.
The synchronous µC interface is based on the asynchronous uC interface, plus additional output
synchronization, i.e., it is slightly slower. The SPI PDI achieves the maximum throughput for accesses
with a large number of bytes. The maximum times for the on-chip bus interfaces (Avalon/OPB/PLB)
are slightly better, because there is no need of synchronization (the throughput degrades with smaller
access width and with a faster bus clock), although the average throughput is similar.
In most situations, the PDI performance is sufficient, at least if the read and write accesses are
properly grouped and timed in relation to the network cycle time.