BECKHOFF ET1100 - Manual (Page 42)

EtherCAT IP Core for Xilinx FPGAs
38 Slave Controller – Application Note FAQ
5.3.3 PlanAhead
5.3.3.1 PlanAhead implementation/floorplaning/analysis is not possible
PlanAhead can only be used pre-synthesis with the EtherCAT IP Core (e.g. for pin planning), because
PlanAhead does not support the security attributes in the generated netlist like ISE. Xilinx is aware of
this issue.
Messages
WARN: [HD-EDIFIN 5] Could not read top design file 'C:\BECKHOFF\ethercat-
v2.04a\reference_designs\EL9800_DIGI_XC3S1200E\EL9800_DIGI_XC3S1200E_VHDL.n
gc' because ngc2edif command failed with the following message:
ERROR:NetListWriters:415 - The design contains secured core(s). Creation of
the
output netlist is prohibited.
ERROR: Failed to open design - please see the console for details