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AMETEK DCS-E 3kW Series User Manual

Page 76

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Theory of Operation

Sorensen DCS-E Series 3kW Supplies

5-6

M362295-01 Rev C

Diodes CR14 and CR15 rectify the output from T2 and resistors R3 and R11-3 scale the signal
before it is input to the positive input of the current sense amplifier at pin 4 of U1. Slope
compensation for PWM output duty cycles above 50% is obtained by injecting the timing
capacitor ramp into the same input through transistor Q1, capacitor C3, and resistors R4 and
R9.

The comparator circuit monitors the PWM error and current sense amplifier outputs and
terminates the PWM output pulse when the current amplifier output signal reaches the error
amplifier reference level. The oscillator circuit provides the 60 kHz timing signals for the PWM.

The sync circuit is used to synchronize the switching frequency of the A3 PWM to that of the
A2 auxiliary supply to reduce noise related switching problems. The circuit consists of
phase-locked loop (PLL) U2 and its related components. An optically-coupled sync signal
(approximately 60 kHz) from the A2 auxiliary circuit oscillator is applied to one input of the PLL
phase comparator at pin 3. The other input, at pin 14, comes from the A3 PWM oscillator timing
capacitor (C7) via capacitor C8. The output of the phase comparator (at U2, pin 2) is connected
to the PWM oscillator timing resistor R14 via resistor R18 and the low pass filter formed by R19
and capacitor C15. The comparator output controls the charging rate of the PWM timing
capacitor, thereby synchronizing the two signals. The PLL also serves to shut down the PWM
whenever the sync signal from the A2 PCB is absent by applying a high signal from U2 pin 10
through diode CR2 to the shutdown input of the PWM at pin 16. Whenever the sync signal is
present, the shutdown signal is inhibited by the high signal at pin 5 of U2.

The gate drive signal for the main switching transistors is supplied by drive transformer T1.
The primary of T1 is driven by the output from PWM at pins 11 and 14 through FETs Q2-7. In
addition to providing the required drive signals, transformer T1, along with the main power
transformer, current feedback transformer T2, and optocoupler U15 on the A2 PCB, provide the
isolation between the power supply input and output.

The primary of the power transformer is driven by the main switching transistors, Q8-11 IGBTs
(insulated gate bipolar transistors) which are configured as a full bridge. The power transistors
are switched ON and OFF in pairs by drive transformer T1, with Q8 and Q10 forming one pair
and Q9 and Q11 the other pair. This paired switching action reverses the polarity of the signal
applied to the transformer primary to produce a 30 kHz AC waveform on its input. Capacitor
C25 and resistor R35 form a snubber across the power transformer primary winding. Each
power transistor has a collector-to-emitter snubber consisting of a resistor, a diode, and a
capacitor.

5.3.4

Power Transformer, Output Rectifiers, Output Filter Inductor
and Capacitor, and Down Programmer Circuit (A4 PCB,
A7 PCB, A8 PCB, and Power Stage Assembly)

The output of the power transformer is rectified using one of two rectifier output configurations:

Full wave center tap (8 to 80V models), or

Full wave bridge (150V model)

RC snubbers across each rectifier (also across the entire secondary of the transformer on some
models) and tape-wound toroids on each transformer secondary lead are used to suppress
transients. The rectifier output is filtered by capacitors C701-711 on the A7 PCB, capacitors