Zilog Z8F0130 - Manual (Page 75)

eZ8
™
CPU Core
User Manual
UM012820-0810 eZ8
™
CPU Instruction Set Summary
60
AND dst, src dst
 dst AND src
r r 52 – * * 0 – – 2 3
r Ir 53 2 4
R R 54 3 3
R IR 55 3 4
R IM 56 3 3
IR IM 57 3 4
ANDX dst,
src dst
 dst AND src
ER ER 58 – * * 0 – – 4 3
ER IM 59 4 3
ATM Block all interrupt
and DMA requests
during execution of
the next 3
instructions 2F – – – – – – 1 2
BCLR bit, dst dst[bit]
 0
r E2 – – – – – – 2 2
BIT p, bit, dst dst[bit]
 p
r E2 – – – – – – 2 2
BRK Debugger Break 00 – – – – – – 1 2
BSET bit, dst dst[bit]
 1
r E2 – – – – – – 2 2
BSWAP dst dst[7:0]
 dst[0:7]
R D5 X * * 0 – – 2 2
BTJ p, bit,
src, dst if src[bit] = p

PC
 PC + X
r F6 – – – – – – 3 3
Ir F7 3 4
BTJNZ bit,
src, dst if src[bit] = 1

PC
 PC + X
r F6 – – – – – – 3 3
Ir F7 3 4
Table 20. eZ8 CPU Instruction Summary (Continued)
Assembly

Mnemonic
Symbolic
Operation
Address
Mode
Op
Code(s)
(Hex)
Flags
Fetch
Cycles
Instr.
Cycles dst src C Z S V D H