Zilog Z8F0130 - Manual (Page 35)

eZ8
™
CPU Core
User Manual
UM012820-0810 Address Space
20
Linear Addressing of Register File
Using 12-bit linear addressing, the eZ8 CPU can directly access any 8-bit
registers or 16-bit register pairs within the 4096B Register File. The
instructions that support 12-bit addressing allow direct register access to
most registers without requiring a change to the value of the Register
Pointer (RP). To accommodate the increase in the register address space
relative to the Z8

architecture, new Extended Addressing instructions
are added to allow easier register access across page boundaries.
Page Mode Addressing of Register File
In Page mode, the Register File is divided into sixteen 256-Byte register
Pages. The current page is determined by the Page Pointer value,
RP[3:0] . Registers can be accessed by Direct, Indirect, or Indexed
Addressing using 8-bit addresses. The full 12-bit address is provided by
{RP[3:0], Address[7:0]} . All 256 registers on the current page can
be referenced or modified by any instruction that uses 8-bit addressing. To
change to a different page, use the Set Register Pointer (SRP) instruction
to change the value of the Register Pointer. (Load instructions, LD or
LDX, can also be used but require more bytes of code space).
Working Register Addressing of Register File
Each Register File page is logically divided into 16 Working Register
Groups of 16 registers each. The Working Registers within each Working
Register Group are accessible using 4-bit addressing. The high nibble of
the eZ8 CPU Register Pointer (RP) contains the base address of the active
Working Register Group, referred to as the Working Group Pointer. When
accessing one of the Working Registers, the 4-bit address of the Working
Register is combined within the Page Pointer and the Working Group
Pointer to form the full 12-bit address
{RP[3:0], RP[7:4],
Address[3:0]} . Figure 4 on page 21 displays this operation.