Zilog Z8F0130 - Manual (Page 18)

eZ8
™
CPU Core
User Manual
UM012820-0810 Architectural Overview
3
4. Present the Op Code and operands to the Instruction State Machine.
The Fetch Unit is pipelined and operates semi-independently from the rest
of the eZ8 CPU.
Execution Unit
The eZ8 CPU Execution Unit is controlled by the Instruction State
Machine. After the initial operation decode by the Fetch Unit, the Instruc-
tion State Machine takes control and completes the instruction. The
Instruction State Machine performs register read and write operations,
and generates addresses.
Instruction Cycle Time
The instruction cycle times varies from instruction to instruction, allow-
ing higher performance given at a specific clock speed. Minimum instruc-
tion execution time for standard CPU instructions is two clock cycles
(only the BRK instruction executes in a single cycle). Because of the vari-
ation in the number of bytes required for different instructions, delay
cycles can occur between instructions. Delay cycles are added any time
the number of bytes in the next instruction exceeds the number of clock
cycles the current instruction takes to execute. For example, if the eZ8
CPU executes a 2-cycle instruction while fetching a 3-byte instruction, a
delay cycle occurs because the Fetch Unit has only two cycles to fetch
three bytes. The Execution Unit is idle during a delay cycle.
Program Counter
The Program Counter contains a 16-bit counter and a 16-bit adder. The
Program Counter monitors the address of the current memory address and
calculates the next memory address. The Program Counter increments
automatically according to the number of bytes fetched by the Fetch Unit.
The 16-bit adder increments and handles Program Counter jumps for rela-
tive addressing.