Zilog Z8F0130 - Manual (Page 195)

eZ8
™
CPU Core
User Manual
UM012820-0810 LDWX Instruction
180
Attributes
Escaped Mode Addressing
Address mode ER for the source or destination can specify a working reg-
ister with 4-bit addressing.
If the high byte of the source or destination address is EEh ( 11101110b ),
a working register is inferred. For example, the operand EE2h selects
Working Register R2. The full 12-bit address is provided by {RP[3:0],
RP[7:4], 2h} .
To access registers on Page Eh (addresses E00h to EFFh ), set the Page
Pointer, RP[3:0], to Eh and set the Working Group Pointer, RP[7:4] , to
the preferred Working Group.
Mnemonic
Destination,
Source
Op
Code
(Hex)
Operand 1 Operand 2 Operand 3
LDWX ER1, ER2 1F E8 ER2[11:4] {ER2[3:0],
ER1[11:8]} ER1 [7:0]