Zilog Z8F0130 - Manual (Page 22)

eZ8
™
CPU Core
User Manual
UM012820-0810 Architectural Overview
7
Zero Flag
For arithmetic and logical operations, the Zero (Z) flag is 1 if the result is
0. Otherwise, the Zero flag is 0. If the result of testing bits in a register is
00h , the Zero flag is 1; otherwise, the Zero flag is 0. Also, if the result of
a rotate or shift operation is 00h , the Zero flag is 1; otherwise, the Zero
flag is 0.
Sign Flag
The Sign (S) flag stores the value of the most-significant bit of a result
following an arithmetic, logical, rotate or shift operation. For signed num-
bers, the eZ8 CPU uses binary two’s complement to represent the data
and perform the arithmetic operations. A 0 in the most significant bit
position (Bit 7) identifies a positive number; therefore, the Sign flag is
also 0. A 1 in the most significant position (Bit 7) identifies a negative
number; therefore, the Sign flag is also 1.
Overflow Flag
For signed arithmetic, rotate or shift operations, the Overflow (V) flag is 1
when the result is greater than the maximum possible number (>127) or
less than the minimum possible number (<–128) that can be represented
with 8-bits in two’s complement form. The Overflow flag is 0 if no over-
flow occurs. Following logical operations, the Overflow flag is 0.
Following addition operations, the Overflow flag is 1 when the operands
have the same sign, but the result has the opposite sign. Following sub-
traction operations, the Overflow flag is 1 if the two operands are of
opposite sign and the sign of the result is same as the sign of the source.
Following rotation operations, the Overflow flag is 1 if the sign bit of the
destination operand changed during rotation.
Decimal Adjust Flag
The Decimal Adjust (D) flag is used for Binary-Coded Decimal (BCD)
arithmetic operations. Because the algorithm for correcting BCD opera-
tions is different for addition and subtraction, this flag specifies the type