Zilog Z8F0130 - Manual (Page 48)

eZ8
™
CPU Core
User Manual
UM012820-0810 Interrupts
44
writes a 1 to bit 5 of Interrupt Request Register 1. If this interrupt at bit 5
is enabled and there are no higher priority pending interrupt requests,
program control transfers to the interrupt service routine specified by the
corresponding Interrupt Vector.
For more information on Interrupt Controller and Interrupt Request
Registers, refer to the Zilog Product Specification specific to your Z8
Encore! device.