Zilog Z8F0130 - Manual (Page 65)

eZ8
™
CPU Core
User Manual
UM012820-0810 eZ8
™
CPU Instruction Set Summary
50
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the
operands, condition codes, status flags, and address modes are
represented by a notational shorthand as described on
Table 10 .
Table 10. Notational Shorthand
Notation Description Operand Range of Operand
b Bit b 0 to 7 (000b to 111b).
cc Condition Code – See the Condition Codes on page 8.
DA Direct Address Addrs 0000h to FFFFh.
ER Extended Addressing
Register Reg 000h to FFFh.
IM Immediate Data #Data Data is a number between 00h to FFh.
Ir Indirect Working
Register @Rn n = 0–15.
IR Indirect Register @Reg 00h to FFh.
Irr Indirect Working
Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14.
IRR Indirect Register Pair @Reg 00h to FEh.
p Polarity p p is a single-bit binary value of either 0b or
1b.
r Working Register Rn n = 0–15.
R Register Reg 00h to FFh.
RA Relative Address X Index in the range +127 to –128, which is
an offset relative to the address of the next
instruction.
rr Working Register Pair RRp p = 0, 2, 4, 6, 8, 10, 12, or 14.