Zilog Z8F0130 - Manual (Page 42)

eZ8
™
CPU Core
User Manual
UM012820-0810 Interrupts
38
Interrupts
Interrupt requests (IRQs) allow peripheral devices to suspend CPU
operation and force the CPU to start an interrupt service routine (ISR).
The interrupt service routine exchanges data, status information, or
control information between the CPU and the interrupting peripheral.
When the service routine finishes, the CPU returns to the previous
operation.
The eZ8
™
CPU supports both vectored-and polled-interrupt handling.
Interrupts are generated from internal peripherals, external devices
through the port pins, or software. The Interrupt Controller prioritizes and
handles individual interrupt requests before passing them on to the eZ8
CPU.
The interrupt sources and trigger conditions are device dependent. Refer
to the Zilog Product Specification specific to your Z8 Encore!
®
device to
determine available interrupt sources (internal and external), triggering
edge options, and exact programming details.
Interrupt Enable and Disable
Interrupts are globally enabled and disabled by executing the Enable
Interrupts (EI) and Disable Interrupts (DI) instructions, respectively.
These instructions affect the global interrupt enable control bit in the
Interrupt Controller. Enable or disable the individual interrupts using
control registers in the Interrupt Controller. Refer to the Zilog Product
Specification specific to your Z8 Encore! device for information on the
Interrupt Controller.