Altera Cyclone IV GX Transceiver Starter Board User Manual
Page 7

Chapter 1: Overview
1–3
Board Component Blocks
© March 2010 Altera Corporation
Cyclone IV GX Transceiver Starter Board Reference Manual
■
General user I/O
■
LEDs and display
■
Four FPGA user LEDs
■
One configuration done LED
■
One max error LED
■
Five Ethernet status LEDs
■
One USB status LED
■
One power status LED
■
Two PGM LEDs
■
A two-line character LCD display
■
Push-Button switches
■
One CPU reset push-button switch
■
One MAX II configuration reset push-button switch
■
One PGM configure push-button switch (configure the FPGA from flash
memory)
■
One PGM select push-button switch (select image to load from flash
memory)
■
Two general user push-button switches
■
DIP switches
■
Board setting DIP switch
■
Configuration setting DIP switch
■
Power supply
■
9-V – 16-V DC input
■
2.5-mm barrel jack for DC power input
■
On/Off slide power switch
■
On-Board power measurement circuitry
■
Mechanical
■
6.6” x 2.713” board
■
PCI Express chassis or bench-top operation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)