Altera Cyclone IV GX Transceiver Starter Board - Manual (Page 16)

2–8 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Cyclone IV GX Transceiver Starter Board Reference Manual © March 2010 Altera Corporation
Table 2–6 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
FSML_D3 A7 F9 FSML bus data
FSML_D4
2.5-V
B7 E13 FSML bus data
FSML_D5 C8 F10 FSML bus data
FSML_D6 A6 F11 FSML bus data
FSML_D7 B6 G9 FSML bus data
FSML_D8 A5 G10 FSML bus data
FSML_D9 B5 A12 FSML bus data
FSML_D10 C7 A11 FSML bus data
FSML_D11 A4 B11 FSML bus data
FSML_D12 B4 B10 FSML bus data
FSML_D13 C4 C11 FSML bus data
FSML_D14 C6 C12 FSML bus data
FSML_D15 B3 C8 FSML bus data
CONF_DONE_LED T11 — FPGA configuration done LED
MAX_ERROR T8 — FPGA configuration error LED
MAX_RESETn M9 — MAX II reset push-button switch
MAX_CSn T12 L5 MAX II chip select
PGM_CONFIG R10 — Loads flash memory image identified by the
PGM LEDs
PGM_LED0 T9 — Flash memory PGM select indicator 0
PGM_LED1 R9 — Flash memory PGM select indicator 1
PGM_SEL T10 — Toggles the PGM_LED[0:1] sequence
SENSE_CSn J3 — Power monitor chip select
SENSE_SCK J1 — Power monitor serial peripheral interface (SPI)
clock
SENSE_SDI J2 — Power monitor SPI data in
SENSE_SDO K1 — Power monitor SPI data out
SRAM_BWan C2 L4 FSML bus SSRAM byte write enable
SRAM_BWbn D2 M4 FSML bus SSRAM byte write enable
SRAM_CEn E2 N6 FSML bus SSRAM chip enable
SRAM_ADSCn F2 — FSML bus SSRAM address status controller
SRAM_ADSPn F1 — FSML bus SSRAM address status processor
SRAM_ADVn G2 — FSML bus SSRAM address valid
SRAM_CLK G1 L7 FSML bus SSRAM clock
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 3)
Schematic Signal Name
I/O
Standard
EPM2210
Pin Number
EP4CGX15BF14
Pin Number Description