Altera Cyclone IV GX Transceiver Starter Board - Manual (Page 15)

Chapter 2: Board Components 2–7
MAX II CPLD EPM2210 System Controller
© March 2010 Altera Corporation Cyclone IV GX Transceiver Starter Board Reference Manual
FSML_WEn
2.5-V
C5 A13 FSML bus flash memory write enable
FPGA_CONF_DONE M2 J5 FPGA configuration done
FPGA_CONFIG_D0 N2 A5 FPGA configuration data
FPGA_nCONFIG M1 D5 FPGA configuration active
FPGA_nSTATUS L2 K6 FPGA configuration ready
FPGA_DCLK L1 A4 FPGA configuration clock
JTAG_TCK P3 B3 FPGA JTAG TCK
JTAG_TMS N4 A2 FPGA JTAG TMS
JTAG_FPGA_TDO L6 A1 FPGA JTAG TDO
JTAG_EPM2210_TDO M5 — MAX II JTAG TDO
FPGA_MSEL0 B16 K5 FPGA MSEL0 configuration mode select
FPGA_MSEL1 A15 N3 FPGA MSEL1 configuration mode select
FPGA_MSEL2 B14 L3 FPGA MSEL2 configuration mode select
FSML_A1 P15 A6 FSML bus address
FSML_A2 N15 B6 FSML bus address
FSML_A3 N16 C6 FSML bus address
FSML_A4 M15 A8 FSML bus address
FSML_A5 M16 A7 FSML bus address
FSML_A6 L15 M11 FSML bus address
FSML_A7 L16 N12 FSML bus address
FSML_A8 K15 K10 FSML bus address
FSML_A9 K16 L11 FSML bus address
FSML_A10 J15 M9 FSML bus address
FSML_A11 J16 N10 FSML bus address
FSML_A12 H16 N11 FSML bus address
FSML_A13 H15 H10 FSML bus address
FSML_A14 G16 H12 FSML bus address
FSML_A15 G15 N13 FSML bus address
FSML_A16 F16 M13 FSML bus address
FSML_A17 F15 J13 FSML bus address
FSML_A18 E16 K13 FSML bus address
FSML_A19 E15 L12 FSML bus address
FSML_A20 D16 L13 FSML bus address
FSML_A21 D15 K11 FSML bus address
FSML_A22 C15 K12 FSML bus address
FSML_A23 C14 D13 FSML bus address
FSML_D0 A9 D11 FSML bus data
FSML_D1 A8 D12 FSML bus data
FSML_D2 B8 E10 FSML bus data
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 3)
Schematic Signal Name
I/O
Standard
EPM2210
Pin Number
EP4CGX15BF14
Pin Number Description