Altera Cyclone IV GX Transceiver Starter Board - Manual (Page 31)

Chapter 2: Board Components 2–23
Memory
© March 2010 Altera Corporation Cyclone IV GX Transceiver Starter Board Reference Manual
Table 2–28. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board Reference Description Schematic Signal Name I/O Standard
Cyclone IV GX Device
Pin Number
U12.37 Address bus FSML_A1
2.5-V
A6
U12.36 Address bus FSML_A2 B6
U12.32 Address bus FSML_A3 C6
U12.33 Address bus FSML_A4 A8
U12.34 Address bus FSML_A5 A7
U12.35 Address bus FSML_A6 M11
U12.42 Address bus FSML_A7 N12
U12.43 Address bus FSML_A8 K10
U12.44 Address bus FSML_A9 L11
U12.45 Address bus FSML_A10 M9
U12.46 Address bus FSML_A11 N10
U12.47 Address bus FSML_A12 N11
U12.48 Address bus FSML_A13 H10
U12.49 Address bus FSML_A14 H12
U12.50 Address bus FSML_A15 N13
U12.80 Address bus FSML_A16 M13
U12.81 Address bus FSML_A17 J13
U12.82 Address bus FSML_A18 K13
U12.99 Address bus FSML_A19 L12
U12.100 Address bus FSML_A20 L13
U12.39 Address bus FSML_A21 K11
U12.58 Data bus FSML_D0 D11
U12.59 Data bus FSML_D1 D12
U12.62 Data bus FSML_D2 E10
U12.63 Data bus FSML_D3 F9
U12.68 Data bus FSML_D4 E13
U12.69 Data bus FSML_D5 F10
U12.72 Data bus FSML_D6 F11
U12.73 Data bus FSML_D7 G9
U12.8 Data bus FSML_D8 G10
U12.9 Data bus FSML_D9 A12
U12.12 Data bus FSML_D10 A11
U12.13 Data bus FSML_D11 B11
U12.18 Data bus FSML_D12 B10
U12.19 Data bus FSML_D13 C11
U12.22 Data bus FSML_D14 C12
U12.23 Data bus FSML_D15 C8
U12.86 Output enable FSML_OEn B13