Altera Cyclone IV GX Transceiver Starter Board - Manual (Page 11)

Chapter 2: Board Components 2–3
Board Overview
© March 2010 Altera Corporation Cyclone IV GX Transceiver Starter Board Reference Manual
D2 Load LED Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
D1 Error LED Illuminates when the FPGA configuration from flash memory fails.
D14, D15, D16,
D17, D18 Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D12 Power LED Illuminates when 9-V – 16-V DC power is present.
S7 Configuration settings DIP
switch Sets the configuration mode to either passive serial (flash) or active
serial (EPCS). This switch is located at the bottom of the board.
S4 CPU reset push-button switch Press to reset the FPGA logic.
S3 MAX II reset push-button
switch Press to reset the MAX II CPLD EPM2210 System Controller.
S2 PGM select push-button switch Toggles the PGM LEDs which selects the program image that loads
from flash memory to the FPGA.
S1 PGM configure push-button
switch Configure the FGPA from flash memory based on the PGM LEDs
setting.
Clock Circuitry
X1 125-MHz oscillator 125-MHz crystal oscillator for PCI Express or general use such as
memories. Multiplexed with CLKIN_SMA_P/N signals based on
CLK_SEL
switch value.
X5 50-MHz oscillator 50-MHz crystal oscillator for configuration purpose. This oscillator is
located at the bottom of the board.
J2, J3 Clock input SMAs Drive LVPECL-compatible clock inputs into the clock multiplexer
buffer (U6).
General User Input/Output
D5, D6, D7, D8 User LEDs Four user LEDs. Illuminates when driven low.
S5, S6 User push-button switches Two user push-button switches. Driven low when pressed.
J6 Character LCD Connector which interfaces to the provided 16 character × 2 line LCD
module.
Memory Devices
U12 SSRAM x18 memory Standard synchronous RAM which provides a 2-MB SSRAM port.
U11 Flash x16 memory Synchronous burst mode flash device which provides a 16-MB
non-volatile memory port.
Components and Transceiver Interfaces
J7 RJ-45 connector Provides 10/100/1000 BASE-T Ethernet connection via a Marvell
88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet
MegaCore function in SGMII mode.
U9 Gigabit Ethernet A Marvell 88E1111 PHY device for 10/100/1000 BASE-T Ethernet
connection. The device is an auto-negotiating Ethernet PHY with an
SGMII interface to the FPGA.
U14 PCI Express edge connector Interfaces to a PCI Express root port such as an appropriate PC
motherboard. Made of gold-plated edge fingers for up to ×1 signaling
in Gen1 mode.
Table 2–1. Cyclone IV GX Transceiver Starter Board Components (Part 2 of 3)
Board Reference Type Description