Altera POS-PHY Level 2 and 3 Compiler - Manual (Page 49)

Chapter 3: Functional Description 3–21
Interface Signals
© November 2009 Altera Corporation POS-PHY Level 2 and 3 Compiler User Guide
Preliminary
Figure 3–16 shows the renb signal behavior.
rval PHY to link Receive data valid. rval indicates the validity of the receive data signals. rval
transitions low when a receive FIFO buffer is empty or at the end of a packet. When
rval
is high, rdat, rprty, rmod, rsop, reop, and rerr are valid. When
rval is low, the rdat, rprty, rmod, rsop, reop, and rerr signals are
invalid and must be disregarded.
The rsx signal is valid when rval is low.
rsx PHY to link Receive start of transfer. rsx indicates when the in-band port address is present on
the rdat bus. When rsx is high and rval is low, the value of rdat[7:0] is the
address of the receive FIFO buffer to be selected by the PHY. Subsequent data
transfers on the rdat bus are from the FIFO buffer specified by this in-band
address. For single-port devices, the rsx signal is optional, as the device does not
need to generate in-band addresses. rsx is valid only when rval is not asserted.
In normal conditions rsx indicates a change of address. If the enable signal goes
inactive as the core decides to select the address, you can have rsx going high
while enable is deasserted. When enable gets reasserted, the core may reassert
rsx
with a different address selected. For example, when the core decides to
reselect the same address just before it is asked to go inactive. By default the core
reselects the same address if data is still available (even if less than a burst). When
enable gets de-asserted, the core checks all possible addresses and if another
address reaches the threshold, it selects the new address instead.
Although it does not violate any POS-PHY protocol, some devices may select the
address on the first rsx and not reselect the address on the second rsx.
To avoid this issue use the fixed burst size. For fixed burst sizes, the core waits at
the end of a packet to ensure the presence of data. If no other port has data, the core
reselects the current one after a short pause. Thus the rsx signal gets asserted
when enable goes high (inactive). The rsx signal stays high until the enable goes
active again but the address does not change.
Table 3–10. POS-PHY Level 3 Receive Interface (Part 2 of 2)
Signal Direction Description