Altera POS-PHY Level 2 and 3 Compiler - Manual (Page 21)

Chapter 2: Getting Started 2–9
POS-PHY Level 2 & 3 Walkthrough
© November 2009 Altera Corporation POS-PHY Level 2 and 3 Compiler User Guide
Preliminary
Step 2: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. It allows for fast functional simulation of IP
using industry-standard VHDL and Verilog HDL simulators.
c You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
will create a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. Click Set Up Simulation in IP Toolbench (see Figure 2–12 on page 2–9 ).
2. Turn on Generate Simulation Model (see Figure 2–13 ).
Figure 2–11. Product Order Code
Figure 2–12. IP Toolbench—Set Up Simulation