Functional description, Chapter 3. functional description – Altera POS-PHY Level 2 and 3 Compiler User Manual
Page 29

© November 2009
Altera Corporation
POS-PHY Level 2 and 3 Compiler User Guide
Preliminary
3. Functional Description
The POS-PHY Level 2 and 3 Compiler has two interfaces—an ‘A’ interface and one or
many ‘B’ interfaces.
Table 3–1
shows the possible interfaces.
Figure 3–1
and
3–2
show example interfaces.
1
MegaCore
®
function data flow direction is from source to sink, that is, data flows from
a physical layer (PHY) receive source to a link receive sink. A MegaCore function
must have a minimum of one source and one sink interface.
Table 3–1. Possible Interfaces
‘A’ Interface
‘B’ Interface
PHY level 3 (SPHY or MPHY)
PHY level 2 (SPHY or MPHY)
Link level 3 (SPHY or MPHY)
Link level 2 (SPHY or MPHY)
PHY level 3 (SPHY only)
PHY level 2 (SPHY only)
Link level 3 (SPHY only)
Link level 2 (SPHY only)
Atlantic master (SPHY only)
Atlantic slave (SPHY only)
Figure 3–1. Example MegaCore Function Interfaces
'A' Sink
Interface
FIFO
'B1' Source
Interface
FIFO
MegaCore Function
'B2' Source
Interface
FIFO
'B3' Source
Interface
FIFO
'B
n'' Source
Interface
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)