Altera POS-PHY Level 2 and 3 Compiler - Manual (Page 37)

Chapter 3: Functional Description 3–9
Parameters
© November 2009 Altera Corporation POS-PHY Level 2 and 3 Compiler User Guide
Preliminary
If a parity error is detected on a sink interface port, which has a wider data width than
its corresponding source interface port, the parity output is high on all output words
that correspond to the input word with an error (see
Table 3–2 ).
When a parity error is detected (as the data comes in), but the data width changes
(increases), there are two options—pass through or error.
Pass through—the word that goes out, which contains the erroneous word and a good
word, is flagged with an incorrect parity.
Error—the par signal functionality changes. It does not show parity, but goes high
only when there is an error with the word, that is, it goes high to show where the error
is.
ParErr On Error Pin
When you check this option, the err signal is created, which looks for parity errors in
the entire packet. The err signal can go high at anytime, but is valid only at the end of
the packet (in accordance with the POS-PHY specifications). A high indicates a parity
error somewhere in the packet. A parity error detected on a sink interface is signalled
by setting the err pin at the end of the affected packet on the source interface.
FIFO Buffer Settings
Table 3–3 shows the effect of the FIFO buffer settings for POS-PHY level 3 interfaces.
1 All FIFO buffer parameters are shown in bytes.