Altera POS-PHY Level 2 and 3 Compiler User Manual
Page 18

2–6
Chapter 2: Getting Started
POS-PHY Level 2 & 3 Walkthrough
POS-PHY Level 2 and 3 Compiler User Guide
© November 2009
Altera Corporation
Preliminary
4. Click Next.
5. Select your interface types (see
Figure 2–6
).
a. Select interface ‘A’ using the radio buttons.
b. Choose ‘B’ interfaces using the drop-down menus.
6. Click Next.
7. Choose the interface settings (see
Figure 2–7 on page 2–6
).
1
POS-PHY Level 3 Specification, Issue 4, June 2000 supports an 8- or 32-bit
interface. Additionally this MegaCore function supports a 16-bit interface
for POS-PHY level 3.
1
POS-PHY Level 2 Specification, Issue 5, December 1998 supports a 16 bit
interface. Additionally, this MegaCore function supports 8- and 32-bit
interfaces for POS-PHY level 2.
1
The Atlantic interface can be 8-, 16-, 32-, or 64-bits wide.
Figure 2–6. Select the Interface Types
Figure 2–7. Choose the Interface Settings
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)