Altera Cyclone II PowerPlay Early Power Estimator - Manual (Page 23)

Altera Corporation 3–7
May 2006 PowerPlay Early Power Estimator User Guide For Cyclone II FPGAs
Using the Cyclone II PowerPlay Early Power Estimator
Figure 3–5. Logic Section in the PowerPlay Early Power Estimator Spreadsheet
RAM Blocks
Cyclone II devices feature M4K RAM blocks.
Each row in the RAM section represents a design module where the RAM
block(s) have the same data width, RAM mode, port parameters and
output toggle rate. If some or all of the RAM blocks in your design have
different configurations, enter the information in different rows. For each
design module, you need to enter the number of RAM blocks, the data
width, the RAM mode and the output toggle rate. You must also enter the
following parameters for each port:
■ Clock frequency, in MHz
■ The percentage of time the RAM clocks are enabled
■ The percentage of time the port is writing compared to reading
1
When selecting the RAM block mode, you must know how your
RAM will be implemented by the Quartus II Compiler. For
example, if a ROM is implemented with two ports, it will be
considered a true dual-port memory and not a ROM. Single-port
and ROM implementations only use port A. Simple dual-port
and true dual-port implementations will use port A and port B.