Altera Cyclone II PowerPlay Early Power Estimator - Manual (Page 21)

Altera Corporation 3–5
May 2006 PowerPlay Early Power Estimator User Guide For Cyclone II FPGAs
Using the Cyclone II PowerPlay Early Power Estimator
Figure 3–2. TFF Example
Figure 3–3. 4-Bit Counter Example
Figure 3–4 shows the Resource Usage Summary in the Quartus II
software Compilation Report for a design targeting the Cyclone II device
family. The Compilation Report provides the total number of LUTs and
registers used by the design.
PRN
CLRN
T Q
TFF
clock
V
CC
INPUT
V
CC
OUTPUT
tff output
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
PRN
CLRN
T Q
TFF
V
CC
V
CC
V
CC
V
CC
cout2 cout1 cout0 clock
cout3
OUTPUT
cout0 cout0
OUTPUT
cout3 cout3
OUTPUT
cout2 cout2
OUTPUT
cout1 cout1