Altera Parallel Flash Loader IP - Manual (Page 56)

Document Revision History
Date Version Changes
January 2015 2015.01.23 • Corrected DATA width in PFL IP core With Dual P30 or P33 CFI
Flash Memory Devices figure.
• Corrected Spansion part number for S29JL032H and S29JL032H
from 229JL032H and 229JL032H respectively.
• Added Micron MT28GU512AAA1EGC-0SIT and
MT28GU01GAAA1EGC-0SIT
• Added example of programming PFL using command line.
• Rearranged the supported flash memory device by grouping device
families.
• Added third-party programmer support.
June 2014 2014.06.30 Replaced MegaWizard Plug-In Manager information with IP Catalog.
May 2014 3.2 Updated Table 16 on page 41 to remove Stratix V limitation for the
Enhanced bitstream decompression IP core option.
May 2013 3.1 Updated Table 2 on page 5 to add 28F00BP30 and 28F00BP33.
September 2012 3.0
• Updated manufacturer name from Numonyx to Micron.
• Updated “Implementing Remote System Upgrade with the PFL IP
Core” on page 22, and “Specifications” on page 49
• Updated Table 4 on page 7, Table 10 on page 30, Table 16 on page
41, Table 17 on page 45, and Table 18 on page 50.
• Removed figures.
August 2012 2.1 Updated Table 1.
December 2011 2.0
• Updated “Using Enhanced Bitstream Compression and
Decompression” to include reference.
• Updated Table 1 to include Eon Silicon CFI device EN29GL128
and to remove S29GL-N devices.
• Updated Table 2 to include Micron QSPI device N25Q128.
• Updated “Specifications”
• Updated Table 13 to include FPP x16 and FPP x32 configuration
scheme for Stratix V devices.
• Updated Figure 27.
• Added Figure 31.
• Minor text edits
February 2011 1.1
• Restructured the user guide.
• Added information about the new feature for the Quartus II
software 10.1 release: Support for NAND flash.
56 Document Revision History
UG-01082
2015.01.23
Altera Corporation Parallel Flash Loader IP Core User Guide
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