Altera Parallel Flash Loader IP - Manual (Page 28)

To constrain the synchronous input and output signals in the TimeQuest analyzer, follow these steps:
1. Run full compilation for the PFL design. Ensure that the timing analysis tool is set to
TimeQuest
Timing Analyzer
.
2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch
the TimeQuest analyzer window.
3. In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of
unconstrained parts and ports of the PFL design.
4. In the Report list, under the Unconstrained Paths category, select Setup Analysis, and then click
Unconstrained Input Port Paths.
5. Right-click each synchronous input or output port in the From list or To list and select
set_input_delay for the input port or set_output_delay for the output port, then specify the input
delay or output delay value.
Related Information
Summary of PFL Timing Constraints on page 28
Constraining Asynchronous Input and Output Ports
You can exclude asynchronous input and output ports from the timing analysis of the PFL IP core
because the signals on these ports are not synchronous to a IP core clock source. The internal structure of
the PFL IP core handles the metastability of these asynchronous signals.
To exclude asynchronous input and output ports from the timing analysis, use the
set_false_path
command to ignore these ports during timing analysis.
Note: After you specify all timing constraint settings for the clock signal, on the Constraints menu, click
Write SDC File to write all the constraints to a specific
.sdc . Then, run full compilation for the PFL
design again.
Summary of PFL Timing Constraints
Table 7: PFL Timing Constraints
Type Port Constraint Type Delay Value
Input clock
pfl_clk create_clock
Can be constrained up to the
maximum frequency supported
by the PFL IP core.
Input asynchro‐
nous
pfl_nreset set_false_path
—
fpga_pgm set_false_path
—
fpga_conf_done set_false_path
—
fpga_nstatus set_false_path
—
pfl_flash_access_granted set_false_path
—
pfl_nreconfigure set_false_path
—
28 Constraining Asynchronous Input and Output Ports
UG-01082
2015.01.23
Altera Corporation Parallel Flash Loader IP Core User Guide
Send Feedback