Altera Parallel Flash Loader IP User Manual
Page 5
Manufacturer
Product Family
Data Width
Density (Megabit)
Device Name
(1)(2)
Eon Silicon
Solution
EN29LV
16
16
EN29LV160B
EN29GL
16
32
EN29LV320B
128
EN29GL128
Table 2: Quad SPI Flash Memory Device Supported by PFL IP Core
Manufacturer
Product Family
Density (Megabit)
Device Name
Micron
N25Q 1.8V
128
N25Q128
N25Q 3.3V
Spansion
FL-P
32
S25FL032P
64
S25FL064P
128
S25FL129P
(1)
Spansion has discontinued the Spansion S29GL-N flash memory device family. Altera does not recommend
using this flash memory device. For more information about an alternative recommendation, see related
information.
(2)
The PFL IP core supports top and bottom boot block of the flash memory devices. For Micron flash memory
devices, the PFL IP core supports top, bottom, and symmetrical blocks of flash memory devices.
UG-01082
2015.01.23
Supported Flash Memory Devices
5
Parallel Flash Loader IP Core User Guide
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)