Altera Parallel Flash Loader IP - Manual (Page 22)

image address. Altera recommends that you write-protect the factory image blocks in the flash
memory device.
Implementing Remote System Upgrade with the PFL IP Core
You can achieve the remote system upgrade capabilities with the PFL IP core by controlling the
fpga_pgm[2..0]
and the
pfl_nreconfigure
ports.
To control the
fpga_pgm[2..0]
and the
pfl_nreconfigure
ports, user-defined logic must perform the
following capabilities:
• After FPGA power up, user logic sets the
fpga_pgm[2..0]
ports to specify which page of configuration
image is to be loaded from the flash.
• After the remote host completes the new image update to the flash, user logic triggers a reconfigura‐
tion by pulling the
pfl_nreconfigure
pin low and setting the
fpga_pgm[2..0]
to the page in which
the new image is located. The
pfl_nreconfigure
signal pulsed low for greater than one
pfl_clk
cycle.
• If you have enabled the user watchdog timer, user logic can monitor the
pfl_watchdog_error
port to
detect any occurrence of watchdog time-out error. If the
pfl_watchdog_error
pin is asserted high,
this indicates watchdog time-out error. You can use the user logic to set the
fpga_pgm[2..0]
and pull
the
pfl_nreconfigure
port low to initiate FPGA reconfiguration. The recovery page to be loaded
from the flash memory device after watchdog timer error depends on the
fpga_pgm[2..0]
setting.
Figure 19: Implementation of Remote System Upgrade with the PFL IP Core
Flash Watchdog
timer reset
circuitry
Altera FPGA
Image
update
circuitry
Remote Host
PFL
Watchdog timer reset
User logic
FPP or PS
configuration
pfl_nreconfigure fpga_pgm[2..0]
Altera CPLD
User Watchdog Timer
The user watchdog timer prevents faulty configuration from stalling the device indefinitely. The system
uses the timer to detect functional errors after a configuration image is successfully loaded into the FPGA.
The user watchdog timer is a time counter that runs at the
pfl_clk frequency
. The timer begins
counting after the FPGA enters user mode and continues until the timer reaches the watchdog time out
22 Implementing Remote System Upgrade with the PFL IP Core
UG-01082
2015.01.23
Altera Corporation Parallel Flash Loader IP Core User Guide
Send Feedback