Altera Parallel Flash Loader IP User Manual
Page 43
Options
Value
Description
Time period before
the watchdog timer
times out
—
Specifies the time out period of the watchdog
timer. The default time out period is 100 ms
Ratio between input
clock and DCLK
output clock
1, 2, 4, or 8
Specifies the ratio between the input clock and
DCLK
.
• Ratio 8 means every eight external clocks to
pfl_clk
generate one
fpga_dclk
.
• Ratio 4 means every four external clocks to
pfl_clk
generate one
fpga_dclk
.
• Ratio 2 means every two external clocks to
pfl_clk
generate one
fpga_dclk
.
• Ratio 1 means every one external clock to
pfl_
clk
generate one
fpga_dclk
.
Use advance read
mode
• Normal Mode
• Intel Burst Mode (P30 or
P33)
• Spansion Page Mode (GL)
• Micron Burst Mode
(M58BW)
An option to improve the overall flash access time
for the read process during the FPGA configura‐
tion.
• Normal mode—Applicable for all flash
memory
• Intel Burst mode—Applicable for Micron P30
and P33 flash memory only. Reduces sequential
read access time
• Spansion page mode—Applicable for Spansion
GL flash memory only
• Micron burst mode—Applicable for Micron
M58BW flash memory only
For more information about the read-access
modes of the flash memory device, refer to the
respective flash memory data sheet.
Enhanced bitstream
decompression
• None
• Area
• Speed
Select to enable or disable the enhanced bitstream
decompression block.
• If you select None, the core disables the
enhanced bitstream decompression block.
• If you select Area, the core optimizes the logic
resources used by the enhanced bitstream
decompression block in the PFL IP core.
• If you select Speed, the core optimizes the
speed of the data decompression. You can only
optimize speed if you select FPP as the FPGA
configuration scheme.
Related Information
•
•
Provides more information about pull-up configuring pins for specific Altera FPGA families
UG-01082
2015.01.23
Parameters
43
Parallel Flash Loader IP Core User Guide
Altera Corporation