Altera Parallel Flash Loader IP User Manual
Page 50
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Flash Access Mode
Configura‐
tion Data
Option
Flash Data
Width (bits)
DCLK Ratio = 1, 2, 4, or 8
(9)
FPP Mode
PS Mode
Burst Mode
Normal
4
C
flash
= 4
C
cfg
= DCLK Ratio
C
overhead
= 48
C
flash
= 4
C
cfg
= 8*DCLK Ratio
C
overhead
= 48
8
C
flash
= 2
C
cfg
= DCLK Ratio
C
overhead
= 22*C
access
+8
C
flash
= 2
C
cfg
= 8*DCLK Ratio
C
overhead
= 22*C
access
+8
16
C
flash
= 1
C
cfg
= DCLK Ratio
C
overhead
= 20*C
access
+8
C
flash
= 1
C
cfg
= 8*DCLK Ratio
C
overhead
= 20*C
access
+8
Compressed
and/or
encrypted
4
C
flash
= 4
C
cfg
= 4*DCLK Ratio
C
overhead
= 48
C
flash
= 4
C
cfg
= 8*DCLK Ratio
C
overhead
= 48
8
C
flash
= 2
C
cfg
= 4*DCLK Ratio
C
overhead
= 22*C
access
+8
C
flash
= 2
C
cfg
= 8*DCLK Ratio
C
overhead
= 22*C
access
+8
16
C
flash
= 1
C
cfg
= 4*DCLK Ratio
C
overhead
= 20*C
access
+8
C
flash
= 1
C
cfg
= 8*DCLK Ratio
C
overhead
= 20*C
access
+8
(9)
Ratio between input clock and DCLK output clock. For more information, see related information
50
Specifications
UG-01082
2015.01.23
Altera Corporation
Parallel Flash Loader IP Core User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)