Altera Parallel Flash Loader IP User Manual
Page 14

Figure 9: Micron J3 Flash Memory in 8-Bit Mode
The address connection between the PFL IP core and the flash memory device are the same.
23
22
21
-
-
-
2
1
0
PFL
address: 24 bits
23
22
21
-
-
-
2
1
0
Flash Memory
address: 24 bits
Figure 10: Micron J3, P30, and P33 Flash Memories in 16-Bit Mode
The flash memory addresses in Micron J3, P30, and P33 16-bit flash memory shift one bit down in
comparison with the flash addresses in the PFL IP core. The flash address in the Micron J3, P30, and P33
flash memory starts from bit 1 instead of bit 0.
22
21
20
-
-
-
2
1
0
PFL
address: 23 bits
23
22
21
-
-
-
3
2
1
Flash Memory
address: 23 bits
Figure 11: Spansion and Micron M28, M29 Flash Memory in 8-Bit Mode
The flash memory addresses in Spansion 8-bit flash shifts one bit up. Address bit 0 of the PFL IP core
connects to data pin
D15
of the flash memory.
23
22
21
-
-
-
2
1
0
PFL
address: 24 bits
22
21
20
-
-
-
1
0
D15
Flash Memory
address: 24 bits
14
Mapping PFL and Flash Address
UG-01082
2015.01.23
Altera Corporation
Parallel Flash Loader IP Core User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)