Altera Parallel Flash Loader IP - Manual (Page 37)

intend to program, do not overwrite the Nios II processor image when you program the flash memory
device with other user data.
If you do not want to store the image in the flash memory device, you can store the Nios II image in a
different storage device, for example an enhanced configuration (EPC) device or an erasable program‐
mable configurable serial (EPCS) memory.
In Relationship Between the Four Sections in the Design Example figure above, the Nios II processor and
the PFL IP core share the same bus line to the flash memory device. However, to avoid data contention,
the processor and the IP core cannot access or program the flash memory device at the same time. To
ensure that only one controller (the processor or the IP core), is accessing the flash memory device at any
given time, you must tri-state all output pins from one controller to the flash memory device, while the
other controller is accessing the flash memory device using the
pfl_flash_access_request
and
pfl_flash_access_granted
pins in the PFL IP core.
Table 11: PFL Flash Access Pins and Functions
Pin Description
pfl_flash_access_request
The PFL IP core drives this pin high to request access to the flash
memory device.
pfl_flash_access_granted
The PFL IP core enables the access to the flash memory device
whenever the PFL IP core receives a high input signal at this pin.
Table 12:
pfl_flash_access_request
and
pfl_flash_access_granted
Pins With the Nios II and PFL IP Core
Table lists the methods to use the
pfl_flash_access_request
and
pfl_flash_access_granted
pins to ensure
both processors are not accessing the flash memory device at the same time.
Signal Nios II Processor PFL IP Core
High output signal at
pfl_flash_access_
request
Tri-state all output pins to
the flash memory device.
Connect all input and output pins to the flash
memory device when the
pfl_flash_access_
granted
pin receives a high input.
Low output signal at
pfl_flash_access_
request
Reconnect all pins to the
flash memory device.
Tri-state all output pins to the flash memory device
when the
pfl_flash_access_granted
pin receives
a low input.
Note: The Set bus pins to tri-state when not in use option for the PFL IP core disables the PFL IP core
whenever the
pfl_flash_access_granted
pin is pulled low.
UG-01082
2015.01.23
PFL IP Core In Embedded Systems 37
Parallel Flash Loader IP Core User Guide Altera Corporation
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