Toshiba Equium 8100 - Manual (Page 84)

Specifications
User's Manual A-1
Version
1
Last Saved on 20/sep/01 8:33
Equium 8100D/M – A-APEND.doc – ENGLISH – Printed on 23/sep/01 as AA_800UK
Appendix A
Specifications
This appendix describes the Equium 8100D and 8100M specifications
and build-to-order (BTO) options available at the time this user’s manual
was published. These specifications apply to both the Equium 8100D and
Equium 8100M unless otherwise stated.
Processor
Processor (options) Intel Pentium 4 with 256 KB level 2 cache: CPU
speed depends on build to order configuration.
Other processors may be available later
Level 1 cache Operation : 12K microOP
Data: 8 KB
Bus speed 400MHz front side bus
LSI and CMOS Large scale integrated and complementary
metaloxide semiconductor technology.
Memory
Base memory
(options) 128, 256, or 512 MB SDRAM
Maximum 1536 MB (512MBx 3)
Sockets 3 DIMM sockets total, 2 DIMM sockets available
(128/256/512 MB SDRAM DIMM).
Memory bus speed 133 MHz
Equium 8100D/M
User's Manual A-1