HP XP P9000 for Compatible High Perf FICON Connectivity Software - Manual (Page 74)

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For OPEN-V volumes, Cache Residency cache areas must be defined in logical blocks using
logical block addresses (LBAs), with a minimum size of 512 LBAs (equivalent to 264 KB). In
most cases you will assign an entire open-systems volume for cache residency. If the remaining
cache memory is less than 256 MB, Cache Residency is not available.
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For mainframe volumes, Cache Residency cache areas must be defined on contiguous tracks
with a minimum size of one cache slot (or track) (equivalent to 66 KB) and a maximum size
of one LVI.
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You can prestage the data to the resident cache area. If prestaging is not used, the data will
be loaded into the Cache Residency area when the first “miss” occurs. If prestaging is used,
performance may be affected for a short time while the data is read into Cache Residency
cache.
CAUTION: Prestaging of Cache Residency data should not be performed during peak
activity.
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All write I/Os to Cache Residency data are duplex writes, guaranteeing full data integrity.
The Cache Residency data remains fixed in cache until you manually delete it. Deletion of
Cache Residency cache areas destages any write data to the affected volumes.
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It is possible to expand the amount of Cache Residency cache without canceling the existing
Cache Residency settings. For details, contact HP Technical Support.
Cache Residency system specifications
Specification Item
Mainframe system Open system
3380-3, 3A, 3B, 3C, OPEN-V Supported device emulation
types
3390-3, 3A, 3B, 3C, 3R, 9, 9A, 9B, 9C, L,
LA, LB, LC, M, MA, MB, MC, A OPEN-3, 8, 9, E, L
Virtual LVI volume LUN Expansion (LUSE) volume Supported volume types
Virtual LUN volume
At least one cache slot (or track): Equivalent
to 66 KB.Up to 1 LDEV. For OPEN-V, at least 512 LBAs:
Equivalent to 264 KB Unit of cache area allocation
For other than OPEN-V, at least 96 LBAs:
Equivalent to 66 KB
Per storage system: 16,384 Number of cache areas
Per LDEV: 4,096
Minimum 512 MB Total cache capacity
74 Estimating cache size