Rainbow Electronics DS2172 - Manual (Page 19)

DS2172
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RECEIVE AC TIMING Figure 6
t R t F
t SU1
t SU2
t HD1
t HD2
t WRL
t CP
t CH t CL
RCLK
RDATA
RDIS
RL/LC
TRANSMIT AC TIMING Figure 7
TCLK
TDATA
TDIS
SEE NOTE BELOW
t CP
t CL t CH
t HD
t SU
t DD
t F t R
NOTE: When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the previous
valve until TDIS is low about the rising edge of TCLK.
TRANSMIT AC TIMING FOR THE TL INPUT Figure 8
TCLK
TDATA
TL
t STL
t WTL
t HTL
NOTE: The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the new
pattern (the shaded one) will appear after two TCLK periods.