Rainbow Electronics DS2172 User Manual

Page 11

DS2172

031197 11/20

REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5

PATTERN TYPE

PTR

PLR

PSR3

PSR2

PSR1

PSR0

TINV

RINV

all ones

all zeros

alternating ones and zeros

double alternating ones and zeros

3 in 24

1 in 16

1 in 8

1 in 4

D4 Line Loopback Activate

D4 Line Loopback Deactivate

NOTES FOR TABLES 4 AND 5:

1. PTR = Polynomial Tap Register (address = 05)

2. PLR = Pattern Length Register (address = 04)

3. PSR3 = Pattern Set Register 3 (address = 00)

4. PSR2 = Pattern Set Register 2 (address = 01)

5. PSR1 = Pattern Set Register 1 (address = 02)

6. PSR0 = Pattern Set Register 0 (address = 03)

7. TINV = Transmit Data Inversion Select Bit (EIR.5)

8. RINV = Receive Data Inversion Select Bit (EIR.4)

9. For the 2

–1 pattern, the random pattern actually repeats every (4093 x 2

) + 1046529 bits instead of 2

– 1.

8.0 BIT COUNT REGISTERS

The Bit Count Registers (BCR3 to BCR0) comprise a
32–bit count of bits (actually RCLK cycles) received at
RDATA. BC31 is the MSB of the 32 bit count. The bit
counter increments for each cycle of RCLK when input
pin RDIS is low. The bit counter is disabled during loss
of SYNC. The Status Register bit BCOF is set when this
32–bit register overflows. Upon an overflow condition,

the user must clear the BCR by either toggling the LC bit
or pin. The DS2172 latches the bit count into the BCR
registers and clears the internal bit count when either
the PCR.4 bit or the LC input pin toggles from low to
high. The bit count and bit error count (available via the
BECRs) are used by an external processor to compute
the BER performance on a loop or channel basis.

BIT COUNT REGISTERS

(MSB)

(LSB)

BC31

BC30

BC29

BC28

BC27

BC26

BC25

BC24

BC23

BC22

BC21

BC20

BC19

BC18

BC17

BC16

BCR3

BCR2

BCR1

BCR0

(addr.=08 Hex)

(addr.=09 Hex)

(addr.=0A Hex)

(addr.=0B Hex)