DS26502 T1/E1/J1/64KCC BITS Element
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LIST OF FIGURES
Figure 3-1. Block Diagram ..................................................................................................................... 12
Figure 3-2. Loopback Mux Diagram....................................................................................................... 13
Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 13
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 14
Figure 13-1. Basic Network Connection................................................................................................. 77
Figure 13-2. Typical Monitor Application................................................................................................ 79
Figure 13-3. CMI Coding ....................................................................................................................... 81
Figure 13-4. Basic Interface................................................................................................................... 90
Figure 13-5. Protected Interface Using Internal Receive Termination .................................................... 91
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 93
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 93
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 94
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 94
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 95
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 95
Figure 15-1. 64kHz Composite Clock Mode Signal Format.................................................................... 97
Figure 17-1. JTAG Functional Block Diagram...................................................................................... 100
Figure 17-2. TAP Controller State Diagram ......................................................................................... 103
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................. 108
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................. 108
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................. 108
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................. 109
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 109
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 109
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................. 110
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................. 110
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 114
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 114
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ................................................................ 115
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 117
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 117
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 118
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 118
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 120
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 120
Figure 20-10. Receive Timing, T1, E1, 64KCC Mode .......................................................................... 122
Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode ......................................................................... 124
