Rainbow Electronics DS26502 - Manual (Page 12)

DS26502 T1/E1/J1/64KCC BITS Element
12 of 125
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
RX
LIU
RX
LIU T1/E1 SSM
FRAMER
64KCC
DECODER
CLOCK
- DATA
TX
LIU
T1/E1 SSM
FORMATTER
64KCC
CODER
PLL
CLOCK
MUX
L
O
C
A
L
L
O
O
P
B
A
C
K
M
U
X
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
RCLK
LOF_CCE
RSER
RS_8K
400HZ
PLL_OUT
TCLK
TSER
TS_8K_4
+ DATA
RTIP
RRING
RLOS
RAIS
TTIP
TRING
THZE
TPOSO
TNEGO
JITTER
ATTENUATOR
CAN BE
ASSIGNED TO
RECEIVE OR
TRANSMIT PATH
OR DISABLED
MASTER CLOCK
MCLK
JTAG PORT TSTRST
TCLKO
TX CLOCK
- DATA
+ DATA
JA
ENABLED
AND IN RX
PATH
JA
ENABLED
AND IN TX
PATH
DS26502
JTAG PORT JTAG PORT JTAG PORT
JTDO JTDI JTCLK JTMS JTRST BIS1 BIS0
JA
ENABLED
AND IN RX
PATH
R
E
M
O
T
E
L
O
O
P
B
A
C
K
M
U
X
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
JA CLOCK