Rainbow Electronics DS2130Q - Manual (Page 2)

DS2130Q
041295 2/22
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
5
1
19
15
DT0
DT1
DT2
DT3 O
O
O
O Detect outputs 0-3. These are the four output detect lines that report energy
threshold levels and DTMF tones. DTMF tone detection always has precedence
over energy level reporting.
2 RST I Reset input. When this pin is low, the internal DSP algorithm is in a reset state
for proper initialization. The DS2130 should always be reset for at least
1 ms after each power-up occurrence.
3
4 TM0
TM1 I
I Test mode pins. These pins are used for factory testing and must be tied to GND
for proper operation.
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5 I
I
I
I
I
I Address Select. Provides serial address ID of the DS2130. The states of A0-A5
must match the address sent in the command byte to enable the serial port. A0
= LSB.
12 SPS I Serial Port Select. This pin must be tied to V
CC
for proper operation of the serial
port. The hardware mode is not supported on the DS2130.
13 MCLK I Master processing clock. This is the clock used for the internal DSP engine and
should be in the range of 10.5 - 13 MHz. MCLK can be asynchronous to any other
clock signal on the DS2130. The duty cycle should be nominally 50%.
14 GND - Ground. Tie this pin to the system logic ground.
16 CPXIN I Compressed data in. This is the serial data input for the compressed audio data
sampled on falling edges of CPXCLK during selected time slots. This data is ex-
panded to 8-bit PCM that is output on PCMOUT except in PCM bypass mode.
17 CPXCLK I Compression/expansion side data clock. This is the clock used to sample data
at CPXIN, to output data at CPXOUT and to determine the proper time slot.
CPXCLK must be synchronous with CPXFS. See “Special Clock Requirements”
section for more details.
18 CPXFS I Compression/expansion side frame sync. This input must be an 8 KHz clock
for proper operation. CPXFS must be the same frequency as PCMFS (normally
they are tied together).
20 CPXOUT O Compressed data out. This is the serial data output for the compressed audio
data, updated on rising edges of CPXCLK during selected time slots.
21 SCLK I Serial port clock. This is the clock used to write configuration data to the serial
port registers.
22 SDI I Serial data input. Data source for the serial port registers.
23 CS I Chip select input. This pin must transition high to low before each write operation
to the serial port.
24 PCMOUT O PCM output. This is the output for expanded data which is in the standard 8-bit
PCM u/A-law format. Data is updated on rising edges of PCMCLK.