Rainbow Electronics MAX5965B - Manual (Page 39)

MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
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The CLC_EN enables the large capacitor detection fea-
ture. When CLC_EN is set the device can recognize a
capacitor load up to 150µF. If the CLC_EN is reset, the
MAX5965A/MAX5965B perform normal detection.
AC_TH allows programming of the threshold of the AC
disconnect comparator. The threshold is defined as a
current since the comparators verify that the peak of
the current pulses sensed at the DET_ input exceed a
preset threshold. The current threshold is defined as
follows:
IAC_TH = 226.68µA + 28.33 x NAC_TH
where NAC_TH is the decimal value of AC_TH.
When set low, DET_BY inhibits port power-on if the dis-
covery detection was bypassed in auto mode. When
set high, DET_BY allows the device to turn on power to
a non-IEEE 802.3af load without doing detection. If
OSCF_RS is set high, the OSC_FAIL bit is ignored. A
reset or power-up sets R23h = 04h. Default IAC_TH is
340µA.
Table 27. Switch Mode Register
ADDRESS = 1Fh
SYMBOL BIT R/W
DESCRIPTION
EN_WHDOG 7 R/W A logic-high enables the watchdog function
WD_INT_EN 6 R/W Enables interrupt on SMODE_ bits
Reserved 5 — Reserved
Reserved 4 — Reserved
HWMODE4 3 R/W
Port 4 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE3 2 R/W
Port 3 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE2 1 R/W
Port 2 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE1 0 R/W
Port 1 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
Table 28. Program Register
ADDRESS = 23h
SYMBOL BIT R/W
DESCRIPTION
Reserved 7 — Reserved
Reserved 6 — Reserved
CLC_EN 5 R/W Large capacitor detection enable
DET_BY 4 R/W Enables skipping detection in AUTO mode
OSCF_RS 3 R/W OSC_FAIL reset bit
2 R/W AC_TH[2]
1 R/W AC_TH[1] AC_TH
0 R/W AC_TH[0]
Setting EN_WHDOG (Table 27) high activates the
watchdog counter. When the counter reaches zero, the
port switches to the hardware-controlled mode deter-
mined by the corresponding HWMODE_ bit. A low in
HWMODE_ switches the port into shutdown by setting the bits in register R12h to 00. A high in HWMODE_
switches the port into auto mode by setting the bits in
register R12h to 11. If WD_INT_EN is set, an interrupt is
sent if any of the SMODE bits are set. A reset sets R1Fh
= 00h.