Rainbow Electronics W25Q32 - Manual (Page 30)

W25Q80, W25Q16, W25Q32
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10.2.13 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO
0
, IO
1
, IO
2
and IO
3
and four Dummy
clock are required prior to the data output
.
The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable
bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. To ensure
optimum performance the High Performance Mode (HPM) instruction (A3h) must be executed once,
prior to the Fast Read Quad I/O Instruction.
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode
bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The upper nibble of the Mode
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“x”). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the Mode bits (M7-0) equals “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in figure 13b. This
reduces the instruction sequence by eight clocks and allows the address to be immediately entered
after /CS is asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the next instruction
(after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal
operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal
instructions (See 10.2.28 for detailed descriptions).
Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)