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C control channel, Max9257 ac electrical characteristics – Rainbow Electronics MAX9258 User Manual

Page 5

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MAX9257/MAX9258

_______________________________________________________________________________________

5

Fully Programmable Serializer/Deserializer

with UART/I

2

C Control Channel

MAX9257 AC ELECTRICAL CHARACTERISTICS

(V

CC_

= +3.0V to +3.6V, R

L

= 50Ω ±1%, T

A

= -40°C to +105°C, unless otherwise noted. Typical values are at V

CC_

= +3.3V,

T

A

= +25°C.) (Notes 5, 9)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PCLK_IN TIMING REQUIREMENTS

Clock Period

t

T

14.28

200.00

ns

Clock Frequency

f

CLK

1/t

T

5

70

MHz

Clock Duty Cycle

DC

t

HIGH

/t

T

or t

LOW

/t

T

35

50

65

%

Clock Transition Time

t

R

, t

F

(Figure 7)

4

ns

SWITCHING CHARACTERISTICS

LVDS Output Rise Time

t

R

20% to 80% (Figure 4)

315

370

ps

LVDS Output Fall Time

t

F

20% to 80% (Figure 4)

315

370

ps

t

R1A ,

t

F1A

642

970

1390

t

R2 ,

t

F2

810

1140

1420

Control Transceiver Transition
Time

t

R1B ,

t

F1B

20% to 80% (Figure 16)

290

386

490

ps

Input Setup Time

t

S

(Figure 5)

0

ns

Input Hold Time

t

H

(Figure 5)

3

ns

t

PSD1

Spread off (Figure 6)

(4.55 x t

T) +

11

Parallel-to-Serial Delay

t

PSD2

±4% spread

( 36.55 x t

T) +

11

ns

PLL Lock Time

t

LOCK

Combined FPLL and SPLL; PCLK_IN stable

32,768 x

t

T

ns

Random Jitter

t

RJ

420MHz LVDS output, spread off,
FPLL = bypassed

12

ps

(RMS)

Deterministic Jitter

t

DJ

2

18

- 1 PRBS, SRATE = 840Mbps, 18 bits,

no spread

142

ps (p-p)

SCL/TX, SDA/RX

R

PULLUP

= 10k

Ω

400

Rise Time

t

RS

0.3 x V

CC

to 0.7 x

V

CC

, C

L

= 30pF

R

PULLUP

= 1.6k

Ω

60

ns

Fall Time

t

FS

0.7 x V

CC

to 0.3 x V

CC,

C

L

= 30pF

40

ns

95kbps to 400kbps

100

400kbps to 1000kbps

50

1000kbps to 4250kbps

10

Pulse Width of Spike Suppressed
in SDA

t

SPK

DC to 10Mbps (bypass mode)

10

ns

400kbps

100

Data Setup Time

t

SETUP

4.25Mbps, C

L

= 10pF

60

ns

400kbps

100

Data Hold Time

t

HOLD

4.25Mbps, C

L

= 10pF

0

ns

I

2

C TIMING (Note 8)

Maximum SCL Clock Frequency

f

SCL

4.25

MHz

Minimum SCL Clock Frequency

f

SCL

95

kHz

Start Condition Hold Time

t

HD:STA

(Figure 30)

0.6

µs