Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 8)

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011 www.ti.com
6-17 Interrupt Switching Characteristics
...........................................................................................
105
6-18 Interrupt Timing Requirements ................................................................................................ 106
6-19 General-Purpose Output Switching Characteristics ........................................................................ 106
6-20 General-Purpose Input Timing Requirements .............................................................................. 107
6-21 SPI Master Mode External Timing (Clock Phase = 0)
....................................................................
108
6-22 SPI Master Mode External Timing (Clock Phase = 1)
....................................................................
110
6-23 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 112
6-24 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 113
6-25 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 114
6-26 XTIMING Register Configuration Restrictions
..............................................................................
115
6-27 Valid and Invalid Timing
.......................................................................................................
115
6-28 XTIMING Register Configuration Restrictions .............................................................................. 115
6-29 Valid and Invalid Timing when using Synchronous XREADY ............................................................ 115
6-30 XTIMING Register Configuration Restrictions .............................................................................. 116
6-31 XTIMING Register Configuration Restrictions
..............................................................................
116
6-32 Asynchronous XREADY
......................................................................................................
116
6-33 XINTF Clock Configurations ................................................................................................... 116
6-34 External Memory Interface Read Switching Characteristics ............................................................. 119
6-35 External Memory Interface Read Timing Requirements .................................................................. 119
6-36 External Memory Interface Write Switching Characteristics
..............................................................
120
6-37 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
.......................
122
6-38 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 122
6-39 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 122
6-40 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 122
6-41 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
........................
125
6-42 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
.......................................
125
6-43 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 125
6-44 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 129
6-45 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 130
6-46 DC Specifications
..............................................................................................................
132
6-47 AC Specifications
..............................................................................................................
133
6-48 Current Consumption .......................................................................................................... 133
6-49 ADC Power-Up Delays ........................................................................................................ 134
6-50 Sequential Sampling Mode Timing .......................................................................................... 136
6-51 Simultaneous Sampling Mode Timing
.......................................................................................
137
6-52 McBSP Timing Requirements
................................................................................................
139
6-53 McBSP Switching Characteristics ........................................................................................... 140
6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 142
6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 142
6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
...............................
143
6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
...........................
143
6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 144
6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 144
6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 145
6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
...........................
145
6-62 Flash Endurance Timing
.......................................................................................................
146
6-63 Flash Parameters at 150-MHz SYSCLKOUT .............................................................................. 146
6-64 Flash/OTP Access Timing .................................................................................................... 146
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