Texas Instruments Digital Signal Processor SM320F2812-HT - Manual (Page 73)

TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7−0
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 − 0
Transmitter−Data
Buffer Register
8
SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
1 TX FIFO _1
−−−−−
TX FIFO _15
8
TX FIFO registers
TX FIFO
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _15
SCIRXBUF.7−0
Receive Data
Buffer register
SCIRXBUF.7−0
−−−−−
RX FIFO_1
RX FIFO _0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PE FE OE RX Error
SCIRXST.4 − 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Interrupts
Interrupts
SM320F2812-HT
www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 4-10 shows the SCI module block diagram.
Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2009 – 2011, Texas Instruments Incorporated Peripherals 73
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