Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 66
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
The CAN registers listed in
are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-6. CAN Registers Map
(1)
REGISTER NAME
ADDRESS
SIZE (
×
32)
DESCRIPTION
CANME
0x00 6000
1
Mailbox enable
CANMD
0x00 6002
1
Mailbox direction
CANTRS
0x00 6004
1
Transmit request set
CANTRR
0x00 6006
1
Transmit request reset
CANTA
0x00 6008
1
Transmission acknowledge
CANAA
0x00 600A
1
Abort acknowledge
CANRMP
0x00 600C
1
Receive message pending
CANRML
0x00 600E
1
Receive message lost
CANRFP
0x00 6010
1
Remote frame pending
CANGAM
0x00 6012
1
Global acceptance mask
CANMC
0x00 6014
1
Master control
CANBTC
0x00 6016
1
Bit-timing configuration
CANES
0x00 6018
1
Error and status
CANTEC
0x00 601A
1
Transmit error counter
CANREC
0x00 601C
1
Receive error counter
CANGIF0
0x00 601E
1
Global interrupt flag 0
CANGIM
0x00 6020
1
Global interrupt mask
CANGIF1
0x00 6022
1
Global interrupt flag 1
CANMIM
0x00 6024
1
Mailbox interrupt mask
CANMIL
0x00 6026
1
Mailbox interrupt level
CANOPC
0x00 6028
1
Overwrite protection control
CANTIOC
0x00 602A
1
TX I/O control
CANRIOC
0x00 602C
1
RX I/O control
CANTSC
0x00 602E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x00 6030
1
Time-out control (Reserved in SCC mode)
CANTOS
0x00 6032
1
Time-out status (Reserved in SCC mode)
(1)
These registers are mapped to Peripheral Frame 1.
66
Peripherals
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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