Texas Instruments Digital Signal Processor SM320F2812-HT User Manual
Page 110
t
c(SPC)
+
SPI clock
cycle time
+
LSPCLK
4
or
LSPCLK
(SPIBRR
)
1)
+
t
c(LCO)
+
LSPCLK cycle time
(2)
SGUS062B
–
JUNE 2009
–
REVISED JUNE 2011
Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)
(1) (2) (3)
SPI WHEN (SPIBRR + 1)
SPI WHEN (SPIBRR + 1)
IS EVEN OR
IS ODD AND
NO.
UNIT
SPIBRR = 0 OR 2
SPIBRR
>
3
MIN
MAX
MIN
MAX
1
t
c(SPC)M
Cycle time, SPICLK
4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
–
0.5tc (LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 0)
2
(4)
ns
Pulse duration, SPICLK low
t
w(SPCL)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
–
0.5tc (LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 1)
Pulse duration, SPICLK low
t
w(SPCL)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5tc(LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 0)
3
(4)
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5tc(LCO)
–
10
0.5t
c(SPC)M
–
0.5t
c(LCO)
(clock polarity = 1)
Setup time, SPISIMO data valid
t
su(SIMO-SPCH)M
before SPICLK high (clock
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
polarity = 0)
6
(4)
ns
Setup time, SPISIMO data valid
t
su(SIMO-SPCL)M
before SPICLK low (clock
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
polarity = 1)
Valid time, SPISIMO data valid
t
v(SPCH-SIMO)M
after SPICLK high (clock polarity
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
= 0)
7
(4)
ns
Valid time, SPISIMO data valid
t
v(SPCL-SIMO)M
after SPICLK low (clock polarity
0.5t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
= 1)
Setup time, SPISOMI before
t
su(SOMI-SPCH)M
SPICLK high
0
0
(clock polarity = 0)
10
(4)
ns
Setup time, SPISOMI before
t
su(SOMI-SPCL)M
SPICLK low
0
0
(clock polarity = 1)
Valid time, SPISOMI data valid
t
v(SPCH-SOMI)M
after SPICLK high (clock polarity
0.25t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
= 0)
11
(4)
ns
Valid time, SPISOMI data valid
t
v(SPCL-SOMI)M
after SPICLK low (clock polarity
0.25t
c(SPC)M
–
10
0.5t
c(SPC)M
–
10
= 1)
(1)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(3)
Not production tested..
(4)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
110
Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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