Section 4.9 – Texas Instruments TMS320TCI6486 User Manual
Page 84
MDIO Registers
www.ti.com
4.9
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in
and described in
.
Figure 36. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
16
Reserved
R-0
15
2
1
0
USERINT
Reserved
MASKED
R-0
R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 29. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field
Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
USERINTMASKED
Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1. Writing a 1
will clear the interrupt and writing 0 has no effect.
84
C6472/TCI6486 EMAC/MDIO
SPRUEF8F – March 2006 – Revised November 2010
Copyright © 2006–2010, Texas Instruments Incorporated