Section 5.22 – Texas Instruments TMS320TCI6486 User Manual
Page 118
EMAC Port Registers
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5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in
and described in
Figure 64. Receive Unicast Enable Set Register (RXUNICASTSET)
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Reserved
RXCH7EN
RXCH6EN
RXCH5EN
RXCH4EN
RXCH3EN
RXCH2EN
RXCH1EN
RXCH0EN
R-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
R/WS-0
LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset
Table 58. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RXCH7EN
Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
6
RXCH6EN
Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
5
RXCH5EN
Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
4
RXCH4EN
Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
3
RXCH3EN
Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
2
RXCH2EN
Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
1
RXCH1EN
Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
0
RXCH0EN
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May
be read.
118
C6472/TCI6486 EMAC/MDIO
SPRUEF8F – March 2006 – Revised November 2010
Copyright © 2006–2010, Texas Instruments Incorporated